1. Field of the Invention
The present invention relates to the field of digital signal processing and, more particularly, to a microprocessor structure and a method for implementing digital filter operations.
2. Description of Related Art
The finite impulse response filter (FIR) and inner product are known as the fundamental operation blocks of a digital signal processor (DSP). The FIR operation is provided to process the following equation: ##EQU1##
wherein, N is the order of a filter, x.sub.n is the nth input, y.sub.n is the nth output, c.sub.i (i=0 . . . N-1) is the constant coefficient of the filter. Taking N=4 as an example, we have: EQU y.sub.n =c.sub.0 x.sub.n +c.sub.1 x.sub.n-1 +c.sub.2 x.sub.n-2 +c.sub.3 x.sub.n-3,
while the operation of the next data is: EQU y.sub.n-1 =c.sub.0 x.sub.n+1 +c.sub.1 x.sub.n +c.sub.2 x.sub.n-1 +c.sub.3 x.sub.n-2.
To perform proper operations on each input value in a conventional digital signal processor, the oldest data is overwritten by the next data, and the pointers of the DSP will be moved to the newest data. The positions of the pointers are automatically calculated during the operation. Referring to FIG. 3A, before performing an operation to a first value, the arrangement of the memory is of . . . c.sub.0, c.sub.1, c.sub.3, x.sub.n, x.sub.n-1, x.sub.n-2, x.sub.n . . . , wherein pointer R1 and pointer R2 are respectively pointed to C.sub.O and x.sub.n. Referring to FIG. 3B, before the next operation is performed, the X.sub.n+1, is overwritten by the x.sub.n+1, and the pointer R2 is pointed to x.sub.n+1. When performing the required multiplication operations for N times to each value, an additional address generator 31 is provided to generate a new pointer Rn to perform the multiplication/addition operation for each time. Such operation is performed by the following equation: EQU R2=(R2-Base+i)% N+Base,
wherein, N=4, i=0 . . . N-1, "Base" is a base address in which the x is stored, and R2 is the address of a first data being processed by the current operation.
Accordingly, it is known that the conventional digital signal processor must be provided with additional hardware to perform the operation of updating the content of the pointer for carrying out a multiplication operation during each operation cycle. While performing such operation, three addition/subtraction operations and one modulo operation must be executed, which result in a relatively high hardware cost. Moreover, a microprocessor usually does not have a hardware multiplier so it cannot efficiently provide the operation functions of such kind of digital signal processing. Therefore, considering the hardware cost, there is a need to have a microprocessor which can efficiently implement digital filter operations.